1. Field of Invention
The present invention relates generally to computer systems, and more particularly to techniques for resolving simultaneous predicted branch instructions.
2. Relevant Background
At the heart of the computer platform evolution is the processor. Early processors were limited by the technology available at that time. New advances in fabrication technology allow transistor designs to be reduced up to and exceeding 1/1000th of the size of early processors. These smaller processor designs are faster, more efficient and use substantially less power while delivering processing power exceeding prior expectations.
As the physical design of the processor evolved, innovative ways of processing information and performing functions have also changed. For example, “pipelining” of instructions has been implemented in processor designs since the early 1960's. One example of pipelining is the concept of breaking execution pipelines into units, through which instructions flow sequentially in a steam. The units are arranged so that several units can be simultaneously processing the appropriate parts of several instructions. One advantage of pipelining is that the execution of the instructions is overlapped because the instructions are evaluated in parallel. Pipelining is also referred to as instruction level parallelism (ILP).
A processor pipeline is composed of many stages where each stage performs a function associated with executing an instruction. Each stage is referred to as a pipe stage or pipe segment. The stages are connected together to form the pipeline. Instructions enter at one end of the pipeline and exit at the other end.
Although pipeline processing continued to be implemented in processor designs, it was initially constrained to executing only one instruction per processor cycle. In order to increase the processing throughput of the processor, more recent processor designs incorporated multiple pipelines capable of processing multiple instructions simultaneously. This type of processor with multiple pipelines may be classified as a superscalar processor.
Within a processor, certain types of instructions such as conditional branch instructions may be predicted. Branch prediction hardware within the processor may be designed to provide predictions for conditional branch instructions. Based on the prediction, the processor will either continue executing the next sequential instruction or be directed to a subsequent instruction to be executed.
A superscalar processor utilizing branch prediction hardware may encounter and resolve two or more predicted branch instructions simultaneously within the same clock cycle in the same or separate pipelines. Commonly in such applications, the processor had to wait until it could determine the full resolution of both branch predictions in order to determine the oldest mispredicting branch before taking any remedial steps in case of a misprediction. There exists a need to decouple the selection of a corrected state from determining the oldest mispredicted branch for a high-speed processor encountering multiple branch predictions.